1. Field of the Invention
The present invention relates to a semiconductor device including a first input terminal, a second input terminal, and a first transistor and a second transistor arranged as a pair of differential transistors that convert a voltage difference between the first input terminal and the second input terminal into a drain current difference between the first transistor and the second transistor.
2. Description of the Related Art
FIGS. 2A and 2B are schematic circuit diagrams that show the vicinity of a pair of differential transistors in a conventional semiconductor device that includes a first transistor having a first input terminal, a second transistor having a second input terminal, and the pair of differential transistors that convert a voltage difference between the first input terminal and the second input terminal into a drain current difference between the first transistor and the second transistor. FIG. 2A shows a case where the pair of differential transistors are p-channel type MOSFETs (hereinafter abbreviated to PMOS). FIG. 2B shows a case where the pair of differential transistors are n-channel type MOSFETs (hereinafter abbreviated to NMOS).
First, FIG. 2A is described. A power source terminal 101, to which a power source voltage Vdd that is higher than a voltage at a GND terminal is input, and a constant current source 102 that flows a constant current Ic are arranged in series. One terminal of the constant current source 102 is connected to a source region of a first PMOS 110 and a source region of a second PMOS 111. Further, a substrate of the first PMOS 110 is provided with a first input terminal 104 to which a voltage V1 is input, and a drain region of the first PMOS 110 is provided with a first drain terminal 107. A substrate of the second PMOS 111 is provided with a second input terminal 105 to which a voltage V2 is input, and a drain region of the second PMOS 111 is provided with a second drain terminal 108. Gates of the first PMOS 110 and the second PMOS, 111 are provided with a gate voltage input terminal 106 to which a common gate voltage Vg is input.
In the constant current source 102, a terminal on the current inflow side is connected with the power source terminal 101, and a terminal on the current outflow side is connected with a common node 103. In the first PMOS 110, the source region is connected with the common node 103, the drain region is connected with the first drain terminal 107, a gate electrode is connected with the gate electrode input terminal 106, and a well region is connected with the first input terminal 104. In the second PMOS 111, the source region is connected with the common node 103, the drain region is connected with the second drain terminal 108, the gate electrode is connected with the gate voltage input terminal 106, and the well region is connected with the second input terminal 105. In general, the first PMOS 110 and the second PMOS 111 are of exactly the same structure, and, in the case where the first PMOS 110 and the second PMOS 111 are turned on and the voltage V1 is equal to the voltage V2, the voltages at the respective terminals are set such that a current Id1 that flows out from the first drain terminal 107 and a current Id2 that flows out from the second drain terminal 108 are equal to each other. Thus, a voltage difference xcex94V between the voltage V1 and the voltage V2 is converted into a threshold voltage difference between the first PMOS 110 and the second PMOS 111 which arises from a difference in back gate effect. Further, the threshold voltage difference is converted into a current difference xcex94Id between the current Id1 and the current Id2.
Therefore, the back gate effect of the first PMOS 110 and the second PMOS 111 occurs even when the voltage V1 and the voltage V2 are in the vicinity of the power source voltage Vdd. Thus, a function of converting the voltage difference xcex94V into the current difference xcex94Id is provided even when the voltage V1 and the voltage V2 are in the vicinity of the power source voltage Vdd.
Next, FIG. 2B is described. As shown in FIG. 2B, the structure is composed of a GND terminal 109, the constant current source 102 that flows the constant current Ic, a first NMOS 112, a second NMOS 113, the first input terminal 104 to which the voltage V1 is input, the second input terminal 105 to which the voltage V2 is input, the first drain terminal 107, the second drain terminal 108, and the gate voltage input terminal 106 to which the gate voltage Vg is input. In the constant current source 102, the terminal on the current inflow side is connected with the common node 103, and the terminal on the current outflow side is connected with the GND terminal 109. In the first NMOS 112, the source region is connected with the common node 103, the drain region is connected with the first drain terminal 107, the gate electrode is connected with the gate voltage input terminal 106, and the well region is connected with the first input terminal 104. In the second NMOS 113, the source region is connected with the common node 103, the drain region is connected with the second drain terminal 108, the gate electrode is connected with the gate voltage input terminal 106, and the well region is connected with the second input terminal 105. In general, the first NMOS 112 and the second NMOS 113 are of exactly the same structure, and, in the case where the first NMOS 112 and the second NMOS 113 are turned on and the voltage V1 is equal to the voltage V2, the voltages at the respective terminals are set such that the current Id1 that flows out from the first drain terminal 107 and the current Id2 that flows out from the second drain terminal 108 are equal to each other. Thus, the voltage difference xcex94V between the voltage V1 and the voltage V2 is converted into the threshold voltage difference between the first NMOS 112 and the second NMOS 113 which arises from the difference in back gate effect. Further, the threshold voltage difference is converted into the current difference xcex94Id between the current Id1 and the current Id2.
Therefore, the back gate effect of the first NMOS 112 and the second NMOS 113 occurs even when the voltage V1 and the voltage V2 are in the vicinity of the voltage of the GND terminal. Thus, the function of converting the voltage difference xcex94V into the current difference xcex94Id is provided even when the voltage V1 and the voltage V2 are in the vicinity of the voltage of the GND terminal.
That is, a differential amplifier circuit or the like which adopts the structure of the vicinity of the pair of differential transistors shown in FIG. 2A and in which the current difference xcex94Id is used to amplify the voltage difference xcex94V when input voltages are the voltage V1 and the voltage V2 can effect its function even when the input voltages are in the vicinity of the power source voltage Vdd. Also, a differential amplifier circuit or the like which adopts the structure of the vicinity of the pair of differential transistors shown in FIG. 2B and in which the current difference xcex94Id is used to amplify the voltage difference xcex94V when input voltages are the voltage V1 and the voltage V2 can effect its function even when the input voltages are in the vicinity of the voltage at the GND terminal.
The above-described structure of the vicinity of the pair of differential transistors in the differential amplifier circuit or the like in the conventional semiconductor device has had a problem in that the voltage V1 or the voltage V2, which is the input voltage, can be used only until it becomes a voltage at which a forward direction of a PN junction constituted of the source region and the well region of the PMOS or NMOS that is the differential transistor is turned on.
For example, in the case where the structure of the vicinity of the pair of differential transistors shown in FIG. 2A is adopted for the differential amplifier circuit, the voltage V1 or the voltage V2, which is the input voltage, can not be used when the input voltage is equal to or lower than the voltage at which a forward direction of a PN junction constituted of the source region that is a p-type semiconductor and the well region that is an n-type semiconductor of the first PMOS 110 or the second PMOS 111 is turned on. This is because the current of the constant current source 102 flows out to the first input terminal 104 or the second input terminal 105, and thus, the current Id1 or the current Id2 decreases or vanishes. Therefore, an operation speed of the differential amplifier circuit decreases or the differential amplifier circuit does not operate, and also, the voltage at the first input terminal 104 or the second input terminal 105 fluctuates.
Also, in the case where the structure of the vicinity of the pair of differential transistors shown in FIG. 2B is adopted, the voltage V1 or the voltage V2, which is the input voltage, can not be used when the input voltage is equal to or higher than the voltage at which a forward direction of a PN junction constituted of the source region that is an n-type semiconductor and the well region that is a p-type semiconductor of the first NMOS 112 or the second NMOS 113 is turned on. This is because the current flows into the constant current source 102 from the first input terminal 104 or the second input terminal 105 when the input voltage is the above-described voltage or more, and thus, the current Id1 or the current Id2 decreases or vanishes. Therefore, the operation speed of the differential amplifier circuit decreases or the differential amplifier circuit does not operate, and also, the voltage at the first input terminal 104 or the second input terminal 105 fluctuates.
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a semiconductor device, including a first input terminal, a second input terminal, and a first transistor and a second transistor comprising a pair of differential transistors that a convert a voltage difference between the first input terminal and the second input terminal into a drain current difference between the first transistor and the second transistor, wherein the first transistor and the second transistor have a MOSFET structure including a source region, a drain region, a well region between the source and drain regions, a gate oxide film on an upper surface of the well region, a gate electrode on the gate oxide film, a first conductivity type substrate regions provided under the source region, the drain region, and the well region through a buried oxide film, the first conductivity type substrate region of the first transistor being the first input terminal, and the first conductivity type substrate region of the second transistor being the second input terminal. Accordingly, the first input terminal and the second input terminal are completely insulated from the source region, the drain region, and the well region. Thus, an input voltage range of the first input terminal or the second input terminal can be remarkably widened.